The present invention pertains to the field of integrated circuits. More particularly, the present invention pertains to sharing and recycling charge or sharing charge for a bus.
Many integrated circuits communicate multiple bits of digital data in parallel using an internal data bus having a set of parallel conductors to which multiple circuit functions are connected. In particular, processors have an internal data bus for communicating among circuits such as arithmetic logic units, fetch units, floating point units, and graphics units. As processor clock speeds have increased, there has been greater demand for faster internal bus speeds.
In modern processors, the series resistance and parasitic capacitance (collectively known as the RC distributed load) of relatively long conductors, such as data bus lines, can become a significant factor in the operating performance of the processor because the parasitic resistance-capacitance affects the time required for the conductor to switch from one digital state to the other. Furthermore, as processor circuits become increasingly dense, the cross-sectional area allowable for the data bus conductors decreases, in turn increasing the resistance of the data bus conductors and increasing the time constant of its switching, particularly if the data bus conductor must fully switch between ground and the power supply voltage (i.e., from xe2x80x9crail to railxe2x80x9d).
Of course, the increased RC distributed load of the data bus conductors can be overcome to some degree by increasing the size of the transistors of the drivers (drive transistors) that drive the bus. Increases in the size of transistors runs counter to the desire to efficiently use processor die space by densely populating the die. Furthermore, the incremental gains in speed diminish rapidly beyond a certain driver size. Additionally, where there may be multiple drivers connected to the bus because of each functional circuit""s need to communicate with other circuits, the RC distributed load of the data bus may be very large because of the added capacitance of the drivers themselves. In some cases, the RC distributed load of the data bus may be too great for any reasonably sized driver to meet the desired switching time from rail to rail.
A method for decreasing the switching time from rail to rail has been described in U.S. Pat. No. 5,295,104 to McClure. McClure describes a data bus having data bus conductors placed in parallel with dummy data bus conductors. During the driving of the data bus, each data bus conductor and its corresponding dummy data bus conductor are complementarily charged (i.e., charged to logic complements of each other). Prior to the next cycle, the data bus conductors and the dummy data bus conductors are connected together so that, by way of charge sharing, the true data conductor is charged to a midlevel voltage. To ensure proper charge of the data conductors, each of the dummy data conductors preferably physically resembles one of the data conductors, having substantially the same length and cross-sectional area, and being formed of the same material. Unfortunately, using dummy data conductors that could take up precious space may be an inadequate solution for today""s densely populated integrated circuits, including processors which are routing limited. Additionally, because of the additional need to drive a dummy data conductor the area allocated to drivers has to be increased over the case where only a data conductor is driven.
Also, dummy conductors may waste significant amounts of power and produce unnecessary heat. Power consumption is a major issue in many computer applications, especially mobile computing. Additionally, heat and its dissipation are significant considerations among processor manufacturers because heat may contribute to destructive failures and improper operation.
According to an embodiment of the invention a method of charge sharing is described. The method includes detecting the logic level of two data conductors and generating a sharing signal for sharing charge between the two data conductors.